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| Plerow APL0990.1 www..com PLL Module Description The plerowTM PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB's PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package. Features + 5dBm Output Level at 990.1 MHz Channel Step Size : 100 kHz 2 nd Harmonic : < - 25dBc Spurious Level : < - 70dBc Lock Time : < 10 ms 30mA Current Consumption Strip-line Resonator Specifications Parameter Frequency Range Output Power Supply Voltage Current Consumption Channel Step Size 2 Harmonics Spurious Level Lock Time Reference Frequency Reference Input Level Phase Noise (C / N) @ 1 kHz @ 10 kHz @ 100 kHz Output Impedance Operating Temp. Range Package Type & Size C mm -40 dBc/Hz -80 -103 -120 50 25 SMT, 19.0Wx19.0Lx5.8H 85 nd Unit MHz dBm V mA kHz dBc dBc ms MHz dBm Min. 980.1 2 4.7 Typical 990.1 5 5 30 100 -25 -70 3 10 Max. 1000.1 7 5.3 Website: www.asb.co.kr E-mail: sales@asb.co.kr Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 10 ASB Inc., 4th Fl. Venture Town Bldg., 367-17 Goijeong-Dong, Seo-Gu, Daejon 302-716, Korea More Information -5 2 7 1) Measurement conditions are as follows: T = 25C, VCC = 5.0 V, Freq. = 990.1 MHz, 50 ohm system. Outline Drawing Top View Bottom View Pin Configuration Dimension (mm) A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: 0.2 D A E F I C B Side View 1/1 www.asb.co.kr H G 1 2 3 4 9 13 15 16 Others CLOCK DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground December 2004 |
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